1. Field of the Invention
The present invention relates to systems for reliable data transfer between different devices; more particularly to high speed serial, point-to-point connected bus systems, in which resynchronization of the serial data stream is required.
2. Description of Related Art
In point-to-point connected bus systems, like the IEEE proposed standard P1394, packets of data are transmitted from one device to the next, with the transmitter's clock combined with the data according to any one of plurality of encoding techniques. Between transmissions of packets of data, the clock and data transmissions stop. Thus the receiver is unable to maintain a clock synchronized with other devices on the bus, and must resynchronize the transmission with its local clock. The transmitter and receiver clocks work at the same nominal frequency plus or minus a tolerance, and with an arbitrary phase relationship.
Resynchronization increases the latency of data transfers, by requiring several clock cycles at each station to perform the resynchronization function before retransmission of the data packet to another station along the string, or use of the data packet by the local station. When a given packet is transmitted along a bus through a number of nodes, the resynchronization latency can add up significantly.
Also, in systems in which data and clock transmissions cease between transmissions of packets, it is critically important to detect an end of a packet of data at the receiving station. Prior art systems rely on control fields within the packets of data themselves to indicate the length of the packet and thus when the end of the packet can be expected to occur.
The control fields in the packets of data extend the length of transmissions on the bus by the length of the control field. This can be significant for systems in which there are numerous transmissions which are short enough that the length of the control field indicating the packet length or end-of-packet becomes a significant portion of the actual packet transmitted. Thus, the control field contributes to the latency between a decision to send data to a receiving station, and the actual time the receiving station has the data to use.
Accordingly, it is desirable to provide a high speed serial bus system which uses a low latency resynchronization circuit and which minimizes the latency and complexity involved in end of packet detection.